1. Field of the Invention
The present invention relates to structures of thin-film integrated circuits formed on insulating surfaces and circuit elements used for them, e.g., structures of thin-film transistors (TFTs). Insulating surfaces referred to herein encompass dielectric layers formed on surfaces of semiconductors or metals, as well as surfaces of insulators. That is, integrated circuits and TFTs manufactured according to the present invention include not only those which are formed on insulating substrates consisting, for example, of glass but also those which are formed on an insulator deposited on a semiconductor substrate consisting of a single-crystal silicon or the like.
2. Description of the Related Art
Thin-film semiconductor devices such as TFTs are obtained by forming islands of a substantially intrinsic semiconductor region (active layer) on an insulating surface, then forming a dielectric film as a gate insulator film by CVD or sputtering, and forming gate electrodes on the dielectric film. In another method, the gate electrodes are formed beforehand, and then a gate insulator film and an active layer are deposited over the gate electrodes. In the former case, source/drain regions are formed by diffusing N- or P-type dopants into an intrinsic thin-film semiconductor. The latter method may also utilize dopant diffusion but it is common practice to form a separate N- or P-type semiconductor film.
The prior art TFT has N- or P-type source/drain regions, a substantially intrinsic channel region, a gate insulator film, and a gate electrode. The gate insulator film and gate electrode are deposited on the channel region. Conductive interconnects and electrodes (referred to as source electrode/interconnects and as drain electrode/interconnects) are connected with the source and drain regions, respectively, to permit electrical connections with the outside. The TFT is controlled by three terminals comprising these source and drain electrodes plus the gate electrode.
In some circuits, it is impossible to clearly distinguish between source and drain regions. In the following description, therefore, the source and drain regions are not discerned by the circuit but rather can be set arbitrarily. That is, an n- or p-type region connected with a terminal which is not a region arbitrarily defined as a source region is defined as a drain region. In recent years, it has been attempted to fabricate an active layer from a crystalline semiconductor instead of an amorphous semiconductor because there is a need to increase the field mobility of the TFT.
The greatest problem with TFTs using such non-single crystal semiconductors, especially non-single-crystal semiconductors (e.g., polysilicon) having crystallinity, is that the leakage current (off current) is large. In particular, when no voltage is applied to the gate electrode, or when a reverse voltage is applied (i.e., in an unselected or off state), no channel (current path) is created. Therefore, no electric current should flow. In practice, however, currents more than normally observed leakage current flowing through a single-crystal semiconductor are observed. Accordingly, it is considered that this phenomenon is inherent to the non-single-crystal semiconductor.
Such large leakage current poses problems in applications where dynamic operation (such as charge retention) is required. Furthermore, in applications where static operation is necessitated, the electric power consumption is undesirably increased.
It is expected that TFTs will find extensive application in active matrix circuits typified by liquid crystal displays. In this kind of circuit, the TFTs act as switching transistors for the pixels arranged in rows and columns. For this purpose, it is required that electric charge stored in pixel electrodes and their auxiliary capacitors (retaining capacitors) do not leak. If large leakage current occurs, electric charge cannot be retained for a sufficiently long time.
It has been considered that the leakage current can be reduced effectively by increasing the channel length or reducing the channel width. If this approach is adopted, the absolute value of the leakage current decreases. However, when a voltage is applied to the gate electrode, i.e., in a selected (on) state, the drain current (on current) is also reduced. As a result, the required operation may not be carried out. That is, with this method, the ratio of the drain current to the leakage current (on/off current ratio) cannot be improved.